Process for removing dopant ions from a substrate

ABSTRACT

A process for removing dopant ions from a semiconductor substrate includes exposing the substrate to a non-aqueous organic solvent in liquid and/or vapor form.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a divisional application of U.S. Ser. No.09/971,820, filed Oct. 5, 2001, the contents of which are incorporatedby reference herein in their entirety.

BACKGROUND OF INVENTION

[0002] The present disclosure relates to device fabrication and inparticular, to a process for removing dopant ions from a semiconductorsubstrate.

[0003] In device fabrication, dopant or impurity ions are introducedinto the semiconductor material to alter its electrical conductivity.One technique of introducing dopant ions into the semiconductor materialis with an ion implanter. An ion implanter typically uses a high currentaccelerator tube equipped with steering and focusing magnets to bombardthe surface of the semiconductor material with dopant ions to impart thedesired electrical properties. These dopant ions are implanted into thetop layer of the semiconductor material and just below the surface,changing the conductivity of a precise region. To create a p-typeregion, an acceptor ion such as boron, gallium or indium is implanted.To create an n-type region, a donor ion such as antimony, arsenic,phosphorous or bismuth is implanted.

[0004] As the ions enter the material, they collide with target atomsand come to rest at an average depth below the surface of the substrate.The average depth at which the ions are distributed varies with theimplant energy as well as with the target material and the species ofion being implanted. For a given target material and ion species, higherenergy generally corresponds to a deeper penetration of the ions intothe material. The dose or the total number of ions entering the targetis controlled by monitoring the ion current during implantation as wellas the time of implantation.

[0005] A variation of conventional ion implantation is a plasma ionimmersion process, wherein the material itself is placed directly in theplasma source while applying an accelerating bias (on the order of a fewkV) to the material. This is an attractive alternative to conventionalion implantation techniques as high dose rates (in the range of 10¹⁵/cm²min) can be achieved at lower energies with less cost intensive ionimplantation equipment modification. Typically the target to beimplanted is placed directly in the plasma and then biased to a negativepotential in order to sufficiently accelerate positive ions into thetarget for implantation.

[0006] Gaseous diffusion of dopants is another method employed to formdoped regions. A gas or vapor containing the desired dopants isdeposited onto the wafer and then thermally diffused into the substratesurface, such as by chemical vapor deposition.

[0007] An alternative to ion implantation and gaseous diffusionprocesses is the use of a doped dielectric film as a dopant diffusionsource. In this alternative approach, a doped dielectric film such asboron silicate glass or arsenic silicate glass, is deposited onto asubstrate and used as a source of dopant ions which are diffused intothe substrate to form doped regions. For example, doped dielectric filmsare deposited at temperatures less than 500° C. in a deposition chamber,and subsequently heated at temperatures greater than 500° C. in adifferent chamber, such as an annealing furnace, to perform the dopantdiffusion to form the doped region.

[0008] All of the above described processes for introducing dopant ionshave a propensity for forming dopant ions at the surface. Depending onthe device properties, the presence of dopant ions at the surface may bedeleterious to device performance. Control of the dopant ions iscritical to device performance because, as noted, diffusing orimplanting dopant ions changes the electrical characteristics of thesemiconductor material. Diffusion or implantation of the ions intoundesired areas or regions can detrimentally affect device performance.For example, diffusion or implantation of arsenic dopant ions into ashallow trench isolation region can cause parasitic lateral leakage.Shallow trench isolation regions are typically fabricated into theintegrated circuit to isolate neighboring devices. Leakage underneaththe shallow trench isolation region from one device to another isexacerbated by the presence of dopant ions, thereby detrimentallyaffecting device performance. Another example of damage caused by ionsimplanted or diffused into undesired areas may occur during thefabrication of vertical DRAM cell array devices. In the vertical DRAMcell, the sidewalls of the isolation trench are used as the channel ofthe array device. The presence of dopant ions in the sidewalls, e.g.,arsenic ions, would undesirably create large fluctuations on the arraydevice threshold voltage. The noted examples are exemplary only and areused to highlight the potential problems caused by the presence ofunwanted dopant ions in the semiconductor material.

[0009] Cleaning methods are frequently employed during the fabricationprocess to remove contaminants and residues from the wafer resultingfrom the various processing steps. These cleaning processes aregenerally aqueous based and are optimized for removing inorganic,organic and/or particulate matter. The so-called “RCA clean” has beenthe standard cleaning sequence utilized by the industry for cleaningsilicon wafers for the past two decades. An RCA clean process comprisesa multitude of steps that may be implemented in whole, or in part, atvarious stages during manufacture of the semiconductor circuit.

[0010] The RCA process includes a so-called “piranha” cleaning step. Thepiranha cleaning step typically comprises dipping the wafers in aninorganic oxidant, such as a solution containing sulfuric acid andhydrogen peroxide. This step is intended to remove organic material froma surface of the semiconductor article. A typical piranha cleaningsolution would comprise hydrogen peroxide (H₂O₂) and sulfuric acid(H₂SO₄) in a ratio of about 1:5 to about 1:50 (hydrogenperoxide:sulfuric acid). The wafers are then rinsed with deionizedwater. The deionized water rinse typically occurs at room temperatures,commonly from about 18° C. to about 23° C. Preferably, the rinseutilizes water with a high resistivity, such as from about 10megohms-centimeter to about 18 megohms-centimeter.

[0011] The wafers are then subjected to a so-called “HF clean”. The HFclean is typically used to remove an oxide film from the surfaces of thesemiconductor wafers. Such oxide film may be formed, for example, duringthe above-discussed piranha clean or due to exposure of thesemiconductor wafer or other article to air or other sources of oxygen,e.g., hydrogen peroxide. The HF clean typically involves dipping thewafers in a solution of water and hydrofluoric acid, with thewater:hydrogen fluoride ratio commonly being in the range of fromapproximately 1000:1 to approximately 100:1. The wafers are then rinsedwith deionized water to remove hydrogen fluoride and various materialsloosened from the surface of the wafer.

[0012] The wafers may then be subjected to a so-called “Standard Clean1” step, commonly referred to as an “SC1” step. The SC1 step isprincipally directed to removing various particulate materials from thesemiconductor surfaces which can more easily attach as a result of thesurface being made hydrophobic by the hydrogen fluoride cleaning stepexplained above, step 1C. In a typical SC1 step, the wafers aresubmerged in a solution of water, hydrogen peroxide and ammoniumhydroxide (for example 5:1:1 by volume), at temperatures from about 75°C. to about 80° C. for a time of from about 2 minutes to about 15minutes. The wafers are then rinsed with deionized water to remove theSC1 solution from the wafers.

[0013] The wafers may also be subjected to a so-called “Standard Clean2” step, commonly referred to as an “SC2” step. The SC2 step is thoughtto desorb atomic and ionic contaminants from the wafers. In particular,the SC2 step is intended to remove metals deposited on the wafer surfaceduring the HF cleaning step and SC1 step. In a typical SC2 step, thewafers are submerged in a solution of H₂O:HCl:H₂O₂ (for example 6:1:1 byvolume). The SC2 step can be carried out at temperatures which areelevated above fabrication room temperatures. Examples of elevatedtemperatures sometimes used are from about 75° C. to about 80° C. TheSC2 step can be effected for various times, for example for times fromabout 1 to about 10 minutes. The wafers are then subjected to adeionized water rinse, similar to the rinse described above regardingSC1, to remove the above-described SC2 solution from the wafers.

[0014] Conventional cleaning methods generally modify the wafer surfaceto remove contaminants and are not effective for removing dopant ionsfrom the surfaces of the semiconductor substrate.

SUMMARY OF INVENTION

[0015] A method for removing dopant ions from an undesired area of asemiconductor substrate includes exposing the undesired area to anon-aqueous organic vapor, wherein the undesired area includes a surfacecontaining the dopant ions; and removing the vapor and dopant ions fromthe undesired area of the substrate. Exposing the undesired area to thevapor preferably occurs prior to formation of a surface oxide layer inthe undesired area. The dopant ions are selected from the groupconsisting of arsenic, gallium, indium, phosphorous, boron, antimony andbismuth ions. In a preferred embodiment, the vapor ishexamethyldisilizane.

[0016] In another embodiment, a method of cleaning a surface of apartially manufactured integrated circuit subsequent to implantation ordiffusion of dopant ions into the surface includes coating the surfacecontaining dopant ions with a non-aqueous organic solvent. The solventis preferably selected from a group consisting of ketones, polyhydricalcohols, cyclic ethers and esters. The method further includes removingthe solvent and dopant ions from the surface.

[0017] Other embodiments of the invention are contemplated to provideparticular features and structural variants of the basic elements. Thespecific embodiments referred to as well as possible variations and thevarious features and advantages of the invention will become betterunderstood when considered in connection with the detailed descriptionand drawings that follow.

BRIEF DESCRIPTION OF DRAWINGS

[0018]FIG. 1 is a graph showing normalized yields of arsenic ions as afunction of depth for a trench array after exposure to solvent andphotoresist fill.

[0019]FIG. 2 is a graph showing normalized yields of arsenic ions as afunction of depth for a trench array with a node dielectric prior tosolvent exposure and photoresist fill.

[0020]FIG. 3 is a graph showing the amount of arsenic ions present in asolvent layer applied in the form of a photoresist as a function ofdepth into the solvent layer.

DETAILED DESCRIPTION

[0021] A process for removing dopant ions from a semiconductorsubstrate, e.g., wafers, includes exposing the substrate to anon-aqueous organic solvent suitable for removing, extracting and/ordiffusing dopant ions from the substrate. The solvent may be applied inthe form of a liquid or a vapor for a period of time effective toselectively remove the dopant ions. Exposing the wafer to thenon-aqueous organic solvent has unexpectedly been found to effectivelyremove dopant ions from undesired areas or regions in the semiconductorsurface.

[0022] The application of the solvent to wafer surfaces can be performedby wafer spin coating, immersion coating, vapor coating or the like. Theprocess may employ conventional coating equipment commonly utilizedduring device fabrication thus advantageously avoiding specialequipment. For example, non-aqueous organic solvent delivered to thewafer in a vapor state may utilize vapor coating equipment such as avapor priming system of the type utilized for priming wafers prior tophotoresist deposition. These types of vapor priming systems generallyconsist of a primer source and a wafer priming chamber. The primersource may be the solvent in liquid form that is heated to its vaporpoint or alternatively, the liquid solvent is bubbled with nitrogen gasto generate a nitrogen/vapor stream. In the event the solvent is appliedto the substrate as a liquid, the use of standard coating apparatus forcoating photoresist compositions is preferred. In this manner, thesolvent may be applied to the substrate by spin coating, immersioncoating or the like. The invention is not limited to any particularcoating application method in this or any of the following embodiments.

[0023] The solvents employed are preferably non-destructive to thesubstrate, e.g., non-oxidizing, non-reducing and preferably do not causeremoval or modification of the substrate surface. Preferably, thesolvent is an organic compound or a mixture thereof that is a liquid atroom temperature and/or a vapor under vapor forming conditions.Preferred solvents are those normally employed during the manufacture ofthe integrated circuit, e.g., photoresist solvents. Examples of suitablesolvents applied in the form of a liquid include ketone solvents such asacetone, methyl ethyl ketone, cyclohexanone, methyl isoamyl ketone and2-heptanone, polyhydric alcohols and derivatives thereof such asethyleneglycol, ethyleneglycol monoacetate, diethyleneglycol,diethyleneglycol monoacetate, propyleneglycol, propyleneglycolmonoacetate, dipropyleneglycol and dipropyleneglycol monoacetate as wellas monomethyl, monoethyl, monopropyl, monobutyl and monophenyl ethersthereof, cyclic ethers such as dioxane, and ester solvents such asmethyl lactate, ethyl lactate, methyl acetate, ethyl acetate, butylacetate, methyl pyruvate, ethyl pyruvate, methyl methoxypropionate andethyl ethoxypropionate. These organic solvents can be used either singlyor as a mixture of two kinds or more according to need. The solvent mayinclude other components such as components used in formulatingphotoresists. Other suitable solvents applied in the form of a liquidwill be apparent to those skilled in the art in view of this disclosure.

[0024] Examples of suitable solvents applied in the form of a vaporinclude non-aqueous ammonium compounds or an ammonium bearing compounds.Ammonium bearing compounds include those compounds that react with thesurface of the substrate to generate ammonia as a byproduct. Forexample, hexamethyldisilazaane (HMDS) is a compound that is commonlyused in semiconductor manufacturing processes. HMDS is typically used asa primer for increasing adhesion of a photoresist layer to thesubstrate. HMDS reacts by hydrolysis with any silanol groups present onthe substrate surface and generates ammonia as a byproduct. In thismanner, HMDS increases the hydrophobicity of the wafer. For the purposesof removing dopant ions, it is preferred that HMDS is delivered as avapor utilizing conventional vapor priming equipment. Advantageously,this minimizes the expense associated with the process since most, ifnot all, semiconductor fabrication processes employ HMDS as a primer andfurther employ vapor priming equipment as its mode of delivery. Thus,the process can be easily integrated into current semiconductormanufacturing processes.

[0025] The process is effective for removing dopant ions such as boron,gallium or indium antimony, arsenic, phosphorous or bismuth ions. In apreferred embodiment, the process is employed to remove arsenic ionsfrom undesired areas or regions. Preferably, the substrate is heated toincrease the removal efficiency of the dopant ions. For illustrativepurposes only, an increase of about 1.4 times was observed for anarsenic ion removal process utilizing a solvent applied in the form of aphotoresist to the surface. The increase of about 1.4 times was observedwhen the wafer temperature was increased from 110° C. to 215° C. Thephotoresist formulation, deposited to a thickness of about 1.4 microns,is known under the tradename AZ751 and is commercially available fromthe Hoechst Corporation.

[0026] The process overcomes the problems noted in the prior art and canbe implemented to remove dopant ions from any dopant ion containingsurfaces. For example, the process can be used to remove arsenic ions inthe collar region of a trench capacitor. Trench capacitors are generallyused for storing data and are described in U.S. Pat. No. 6,107,135entitled “Method of Making a Semiconductor Memory Device Having a BuriedPlate Electrode” to Kleinhenz et al. In manufacturing trench capacitors,a collar region for the trench capacitor creates a vertical isolationregion between a buried plate and a buried strap. The manufacturingprocess may employ the use of dopant source films, e.g., arsenic glassfilms, that are typically formed on the deep trench surfaces. Parasiticleakage between the plate and strap can occur due to the presence ofarsenic ions in the collar region. The removal process is preferablyutilized after the node nitride is removed from the collar region of thetrench capacitor. Advantageously, the use of the process minimizesparasitic leakage. In another example, the process may be used to removearsenic ions from the surfaces of a shallow trench isolation region(STI). Removing ions from the isolation region surfaces, after the STIhas been etched and prior to surface oxidation, minimizes and/orprevents parasitic lateral leakage from occurring underneath the STIregion. In yet another application, the process may be employed duringthe fabrication of vertical gate DRAM cells. In a vertical gate DRAMcell, the sidewalls of the isolation trench are used as the channel ofthe array device. The presence of dopant ions in the sidewalls, e.g.,arsenic ions, would undesirably create large fluctuations on the arraydevice threshold voltage. Preferably, the cleaning process is utilizedprior to gate oxidation.

[0027] The following examples fall within the scope of, and serve toexemplify, the more generally described methods set forth above. Theexamples are presented for illustrative purposes only, and are notintended to limit the scope of the invention.

EXAMPLE 1

[0028] In this example, the mass profiles of arsenic ions (mass 75)through arrays of deep trenches were measured by Secondary Ion MassSpectrometry (SIMS). The deep trenches are used to form a trenchcapacitor. The trench is typically filled with n+doped poly which servesas one plate of the capacitor (referred to as the storage node). Thesecond plate of the capacitor, referred to as a “buried plate,” isformed by, for example, outdiffusing n+dopants from a dopant source intoa region of the substrate surrounding the lower portion of the trench. Adielectric layer is provided to separate the two plates forming thecapacitor. To prevent or reduce parasitic leakage that occurs along theupper portion of the trench to an acceptable level, an oxide collar ofsufficient thickness is provided therein. An arsenic-silicate glass(ASG) is deposited to form doped glass spacers on the sidewalls of theapertures above the deep trenches. The wafer, including the deeptrenches, was then exposed to a vapor of hexamethyldisilazine and thenfilled with approximately 0.1 microns of photoresist. The arsenic signalwas measured from the surface to a depth of 0.8 microns. The portion ofthe wafer monitored for arsenic ions includes the thickness of thephotoresist, the collar region and the buried plate region. As shown inFIG. 1, an elevated arsenic signal count in the photoresist layer in thecollar region of the deep trench was observed indicating that thearsenic ions diffused from the wafer surface into the photoresist layer.

EXAMPLE 2

[0029] In this example, the mass profiles of arsenic ions through arraysof deep trenches were analyzed as in example 1. A thin dielectric layer,i.e., the node, is deposited onto the arsenic containing surfaces of thewafer prior to the steps of exposing the substrate to the HMDS vapor andphotoresist deposition processes. As shown in FIG. 2, diffusion of thearsenic ions are blocked by the presence of the dielectric layer. Thearsenic signal in the photoresist layer is approximately 100 times lessthan the signal observed in the same region shown in FIG. 1. The resultsdemonstrate that exposing the arsenic containing silicon surfaces to anHMDS vapor effectively removed arsenic ions from the surface of thearray.

EXAMPLE 3

[0030] In this example, silicon wafers were exposed to an arsenic ionimplant dose of 5E13/cm². A solvent in the form of a photoresistformulation was then applied to the wafer surface. Secondary mass ionspectroscopy was employed to determine the arseniuc content in thephotoresist layer. These wafers were compared to control wafers coatedwith the same photoresist formulation that were not exposed to theimplant process. The results are shown in FIG. 3.

[0031] The results clearly show an increase of arsenic ions into thesolvent layer for wafers exposed to the arsenic ion implant dose.

[0032] While preferred embodiments have been shown and described,various modifications and substitutions may be made thereto withoutdeparting from the spirit and scope of the disclosure. Accordingly, itis understood that the present disclosure has been described by way ofillustrations and not limitation.

1. A method of cleaning a surface of a partially manufactured integratedcircuit subsequent to implantation of dopant ions into the surface,wherein the surface contains dopant ions, the method comprising: coatingthe surface containing dopant ions with a non-aqueous organic solventselected from the group consisting of ketones, polyhydric alcohols,cyclic ethers and esters; and removing the solvent and the dopant ionsfrom the surface.
 2. The method according to claim 1, wherein thesurface is a collar region in a deep trench.
 3. The method according toclaim 1, further comprising rinsing the partially manufacturedintegrated circuit with deionized water.
 4. The method according toclaim 1, wherein the solvent is selected from the group consisting ofacetone, methyl ethyl ketone, cyclohexanone, methyl isoamyl ketone and2-heptanone, ethyleneglycol, ethyleneglycol monoacetate,diethyleneglycol, diethyleneglycol monoacetate, propyleneglycol,propyleneglycol monoacetate, dipropyleneglycol and dipropyleneglycolmonoacetate as well as monomethyl, monoethyl, monopropyl, monobutyl andmonophenyl ethers thereof, dioxane, methyl lactate, ethyl lactate,methyl acetate, ethyl acetate, butyl acetate, methyl pyruvate, ethylpyruvate, methyl methoxypropionate, ethyl ethoxypropionate and mixturesthereof.
 5. The method according to claim 1, wherein coating the surfaceoccurs prior to formation of a barrier layer on the surface.
 6. Themethod according to claim 1, wherein the dopant ions are selected fromthe group consisting of arsenic, gallium, indium, phosphorous, boron,antimony and bismuth ions.
 7. The method according to claim 1, furthercomprising heating the surface and removing an increased amount ofdopant ions.
 8. The method according to claim 1, wherein the non-aqueousorganic solvent further comprises a soluble polymer and a solublephotosensitive compound.